The Institute of Electrical and Electronic Engineers (IEEE) standard 1149.1, “Standard Test Access Port and Boundary-Scan Architecture”, provides a system to control and observe boundary pins of a compliant device. During such control and observation, input pin signals may be captured and output pin signals may be preset to test downstream devices. A compliant device includes a Test Access Port (TAP) controller and TAP registers for supporting the standard.
Improper functioning of the TAP registers may lead to ineffective testing of the compliant device. For example, a testing system may improperly evaluate data received from the TAP register if the TAP register corrupts data that is shifted through it. Additionally, if the actual length (i.e., bit size) of the TAP register is not equal to its expected length, any system acting on the output of the register may not function properly. Fabrication, design and/or documentation errors may increase the likelihood of either of these scenarios. Systems for efficiently detecting TAP register size and/or malfunctions are therefore desired.